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SystemC/TLM Semantics for Heterogeneous System-on-Chip Validation

Abstract : SystemC has become a de facto standard for the system-level description of systems-on-a-chip. SystemC/TLM is a library dedicated to transaction level modeling. It allows to define a virtual prototype of a hardware platform, on which the embedded software can be tested. Applying formal validation techniques to SystemC descriptions of SoCs requires that the semantics of the language be formalized. The model of time and concurrency underlying the SystemC definition is intermediate between pure synchrony and pure asynchrony. We list the available solutions for the semantics of SystemC/TLM, and explain how to connect SystemC to existing formal validation tools.
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Contributor : Matthieu Moy Connect in order to contact the contributor
Submitted on : Tuesday, August 12, 2008 - 1:04:54 PM
Last modification on : Thursday, February 3, 2022 - 11:14:34 AM
Long-term archiving on: : Friday, October 5, 2012 - 11:42:43 AM


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  • HAL Id : hal-00311011, version 1
  • PRODINRA : 250084



Florence Maraninchi, Matthieu Moy, Jérôme Cornet, Laurent Maillet-Contoz, Claude Helmstetter, et al.. SystemC/TLM Semantics for Heterogeneous System-on-Chip Validation. 2008 Joint IEEE-NEWCAS and TAISA Conference, Jun 2008, Montréal, Canada. ⟨hal-00311011⟩



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